The present invention generally relates to automated manufacture systems and methods and, more particularly, relates to automated and robotic semiconductor equipment systems and methods, particularly for testing and quality control, and improvements thereto, including reduction of index timing delays and the like.
Automated manufacturing equipment has streamlined the manufacturing process in many industries. Moreover, such automation has increased reliability and results. A downside of automation has been timing delays in equipment operations. Particularly, where expensive manufacturing equipment is involved, delays in operations of the equipment, such as during mechanical movements in transferring devices under test, limit returns on the costs of such equipment because of idle or non-testing use periods during mechanical manipulations, resets, and the like. An impetus in manufacturing technology and operations has, therefore, been to limit times in which costly test equipment is idle and not performing the applicable test function, for example, when robotically substituting next test pieces.
In semiconductor manufacture, semiconductor device test equipment is a costly capital requirement. Conventionally, such test equipment has included a robotic manipulator for handling the devices being tested. This robotic manipulator system is commonly referred to as a “handler” and is typically configured with one or more robotic arms referred to as “manipulators.” The manipulator mechanically picks up a device for testing, inserts the device into an interface test board socket and issues a start-of-test signal to the tester. The tester then conducts a test on the device and returns a test result and an end-of-test signal to the handler which causes the handler to disposition the device to a post-test tray or receptacle for holding tested devices. This process is repeated as long as the handler senses that there are additional devices available for test. This system as a whole is sometimes referred to as a “test cell.”
During the time required for the handler to disposition a device(s) just tested and replace it with the next device(s) to be tested, the tester remains substantially idle. This idle time, sometimes referred to as the “index time” for the particular tester and system, involves mechanical manipulations of the devices awaiting test and having been tested. These mechanical manipulations are limited in speed of operations by various factors, including, for example, physical and speed constraints to ensure that devices to be tested are not damaged, contaminated, dropped, and the like.
The time required to test a device is sometimes referred to as “test time” for a particular device, test, tester, and system. When the system is operational in a manufacturing capacity, it is either indexing during the index time or otherwise testing during the test time.
Previously, test equipment manufacturers have focused efforts to reduce index time on design of manipulation equipment to increase speed of mechanical operations. Although speeds of mechanical operations in handling the test devices have increased significantly over time, there nonetheless remains significant mechanical index time required to manipulate test devices between tests, by the robotic handlers. Moreover, with increased speeds of mechanical manipulation equipment operations, costs increase for the equipment, including calibration, replacement frequency, maintenance, parts, and others. Given the constraints and precautions that must be addressed in speeding mechanical manipulations of many types of test devices and handlers, further speeding of mechanical operations is subject to economic and physical barriers.
In any event, reducing index time can provide greater returns on investments in test equipment, particularly where the test equipment is costly. It would, therefore, be a significant improvement in the art and technology to further reduce index time involved in test operations in manufacturing environments. Particularly in semiconductor manufacture, economic and other gains and advantages are possible if index times are reduced in the testing of semiconductor devices. It would also be an improvement to provide new and improved systems and methods for achieving reduced index times, without requiring substantial changes or new developments in existing mechanical operations of device handlers and similar robotic or automated components for the testing.
For purposes of background understanding, conventional testing systems and operations are now described:
Referring to FIG. 1, a conventional system 100 for testing a device 102 includes a tester 104, an interface board 106 connected to the tester 104 that makes available the tester 104 resources (e.g., testing protocols, signals, and procedures run by the tester) to the device 102 under test, and a robotic handler 108. It is to be understood that the device 102 can be a single device or multiple devices simultaneously connected to the tester and tester resources for concurrent testing operations, but that the singular term “device” is used herein to refer to devices that are so simultaneously connected and concurrently tested. The robotic handler 108 is communicatively connected to the tester 104. The interface board 106 is communicatively connected to the tester 104. The interface board 106 includes one test socket 110 for receiving and maintaining the device 102 during testing.
The test socket 110 provides a physical mechanism that assists the manipulator arm 109 in the alignment of the device 102 under test, so that electrical contact between the device 102 under test and the tester 104 is adequately maintained while the device 102 is undergoing electrical test. Typically the precision of the manipulator arm 109 is too course to provide and maintain proper electrical contact between the device 102 under test and the tester 104 and relevant tester resources, and it is the test socket 110 which provides the mechanics of fine alignment required to maintain proper electrical contact during test.
Furthermore, a single interface board can have more than one test socket. When multiple sockets are present on the interface board, each socket has been typically connected to respective distinct sets of tester resources from a single tester 104. In effect, the tester 104 can perform different tests on each socket, but not the same tests on each socket concurrently. There can be certain exceptions, in special cases, where the tester resources can drive signals from the tester to multiple devices at the same time. Such resources include power supplies, digital drivers, and analog waveform generators. In each case the resource is considered an output resource from the particular tester, and the tester in such use must be specially configured and have functionality required to perform the separate distinct testing in concurrent manner. Most conventional testers do not have such special configuration or functionality and, in any event, any such special testers can be significantly more expensive and/or limited in application when compared to most conventional testers.
The robotic handler 108 mechanically moves and operates to pick up and handle the device 102, from among one or more devices to be tested. Once the device 102 to be tested is picked-up by the manipulator arm 109, the handler 108 controls the transfer of the device 102 into position in the appropriate socket 110 of the interface board 106. The tester 104 then commences to test the device 102. After the test is completed by the tester 104, the handler 108 mechanically removes the device 102 from the socket 110 and transfers the device 102 to a location of tested devices.
In operations of the conventional system 100, a set of devices to be tested are staged at the input to the handler 108 by a human operator. The operator then instructs the handler 108 to begin retrieving devices to be tested and to stage the next available device by inserting it into the test socket 110. Once the handler 108 has sensed that the first device 102 is in place in the test socket 110 and ready for test, the handler 108 issues a start-of-test signal to the tester 104. In response to the start-of-test signal, the tester 104 executes a test program that electrically stimulates, via the test socket 110, the device 102 under test and measures the output response from the device 102. The tester 104 compares the output response to a set of expected response data and judges the results as either a “pass” or a “fail” of the device 102.
If the interface board contains multiple test sockets and the tester is capable of concurrent testing with different tester resources of the tester, as with the certain specialized tester previously mentioned, the tester must query the handler status to determine which test sockets have devices ready for test and which do not. The tester can then ignore failing test results from empty test sockets and test only active test socket sites with devices inserted. Of course, as previously mentioned, such special testers with these capabilities are relatively uncommon, expensive, and limited in application.
Once the test program has concluded testing for the device 102 and a pass/fail determination of the test results has been made by the tester 104, the tester 104 communicates back to the handler 108 the test result data for the device 102 just tested and follows by an end-of-test signal to the handler 108. The handler 108 receives the end-of-test signal from the tester 104, and the handler 108 uses the test results data to disposition the device 102 just tested into an output staging area for tested devices, such as separate holding areas for passing devices and for failing devices, respectively.
If the interface board contains multiple test sockets and the tester is capable of concurrent testing with different tester resources of the tester, as with the certain specialized tester previously mentioned, the tester must communicate results data for each of the active test socket locations that is site specific and the handler must disposition each of the devices accordingly. Again, any such arrangement requires specialized tester and possibly special handler equipment, and these each have the problems of expense and limited applications.
In ongoing operations of the system 100, once the handler 108 has dispositioned the device 102 just tested, the process repeats in succession until there are no additional untested devices remaining to be tested, or until any error condition in the handler status or tester halts operation, or until a human operator intervenes to halt the testing.
In each case of a test in this conventional system 100, the handler 108 individually obtains and transfers the respective device 102 then being tested. During the mechanical operations of the handler 108 in picking up, setting in the socket 110, and locating after test, the tester 104 remains idle without conducting any test. The index time for the system 100 is substantially the time required for the mechanical operations of the handler 108 when removing and dispositioning the tested device and then retrieving and inserting each next successive untested device for testing. The index time also includes any time interval between the end-of-test signal from the tester 104 to the handler 108 and the next start-of-test signal from the handler 108 to the tester 104.
Referring to FIG. 4, a conventional process 400 for testing a device includes a step 402 of initiating a first manipulator. In the step 402, for example, a signal is communicated to a robotic handler having the first manipulator. The signal is communicated by a tester or other source, to indicate to the handler that the first manipulator should initiate actions to obtain and locate a device for testing. The device is, for example, a semiconductor device or any other manufactured part or element that is to be tested by the particular tester.
In a step 404, the first manipulator mechanically moves its arm to retrieve a first device for testing. The first manipulator grips or otherwise retains the first device. Then, in a step 406, the first manipulator mechanically picks-up and manipulates the first device, for example, appropriately orienting the first device for testing. In a step 408, the first manipulator mechanically moves the first device to an interface board connected to the tester and inserts the first device in a socket or other test cell of the interface board.
Once the first device is located in the socket or other test cell, the tester commences a step 412 of testing of the device. Testing can include power test, logic test, and any of a wide variety of other quality control or device conformance tests. The testing may take some period of time for completion, depending on the test being performed. During the testing, the first manipulator maintains the first device in position at the interface board for the test.
When the testing step 412 is completed, the tester signals to the handler and the first manipulator is activated to mechanically remove the device, in a step 414, from the socket or other test cell. The first manipulator then moves the first device to a desired post-test location in a step 416. In a step 418, the first device is released by the first manipulator at the post-test location.
The process 400 then returns to the step 402, in order to repeat the steps with respect to a next test device and a next test of the device. As previously mentioned, the time during the process 400 required for the operations of the first manipulator of the handler to pick-up, move, place, remove and dispense of each device, is referred to as the “index time” for the test system. During the index time of operations of the first manipulator, the tester remains in an idle state in which no test is being conducted. The index time that is required in such process 400 delays and limits the entire process 400.
Referring to FIG. 13, conventional testers include pin electronics cards 1302 that provide for the various tests performable by the tester, both analog and/or digital. Each pin electronics card 1302 contains one or more test resources, represented by the blocks 1302a-c. The test resources of each pin electronics card 1302 can include different, more, less or other elements from those of blocks 1302a-c, which are solely for example purposes, including, without limitation, such as the following:                1. a driver that drives a voltage to an input pin (or pad) on the DUT;        2. a receiver or comparator that measures the voltage on an output pin (or pad) of the DUT;        3. a current load of a 50 Ohm resistive connection to a variable termination voltage and current clamps which change the 50 Ohm resistance to whatever is required to hold the current load at a fixed and programmable value;        4. memory that stores data states (drive and receive), timing, and voltage thresholds;        5. a controller that sequences the drive and receive data to and from the DUT at a programmed rate;        6. fail memory that stores information on when the expected data does not match the actual data measured by the receivers;        7. software that manages the operation of the pin electronics of the card, individually and in synchronization with other tester resources; and        8. a calibration system that measures the length of the communication connection from the pin electronics to the DUT resources on the corresponding pin on the DUT.The pin electronics of the card 1302 can also include test hardware of an analog nature, such as analog to digital converters, digital to analog converters, and time measurement systems. The particular types of test resources of the card 1302 enable testing of the device under test (“DUT”) by the tester.        
Each pin electronics card 1302 includes test resources for one or more tester channels 1304, each tester channel 1304 serving to test, typically, at a single pin of the DUT. As previously mentioned, there are certain special configurations or functionalities where tester resources could drive signals from the tester to multiple pins at the same time; but most conventional testers do not have this capability and, in any event, the capability is significantly more expensive and quite limited in application. So, for purposes of discussion and understanding, the typical circumstance of test resources that drive a single pin of a single device, via a tester channel connected to the single pin of the device, is described herein. (It should be understood, however, that even if a “special capability” situation is presented, the presently disclosed embodiments will provide advantages as those skilled in the art will know and appreciate.)
Referring to FIG. 14, in conjunction with FIG. 13, another functional representation of the foregoing shows various pin electronics cards 1402, each including various respective test resources 1402a-d, with the separate respective tester channel 1404 connecting the applicable test resources 1402a-d to a single pin of a DUT (not shown in detail).
Referring to FIG. 15, conventional testers have pin electronics cards that include relays, such as the AC Relay of the exemplary pin electronics card 1500. The AC Relay, for example, electrically disconnects the test resources of the pin electronics card provided over the tester channel 1504, from a single pin of a DUT (not shown in detail) to which the tester channel 1504 is connected.
Because of the conventional design of testers and pin electronics cards, as just described, index time is consumed in testing because each tester channel can connect to only the single pin. This dictates that the tester channel for the test resources of the pin electronics card can connect for testing to solely a single pin of one DUT at each instant. In testing of each next DUT, therefore, the tester must mechanically connect the tester channel to the same equivalent single pin of the next DUT. This has required that the tester remove a DUT from the socket of the interface board of the tester after testing the DUT, and then place a next DUT in the same test socket of the interface board for performing the test on this next DUT. The tester channel, and test resources of the pin electronics card, remains unused during the mechanical displacement and replacement operations.
From the foregoing description of the conventional system and method for testing devices, it can be readily appreciated and understood that reductions of index time required in the conventional system and method would provide significant advantages. Moreover, it can be appreciated and understood that any reductions that require specialized tester and handler equipment can be inordinately expensive and limited in application.
The present invention provides these and other advantages and improvements, including improvements and nuances in the foregoing respects, without problems and disadvantages previously incurred in practice.